1. Technical Field
The present invention generally relates to VLSI device testing in general, and in particular to testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting built-in self-test (BIST) structures and functions of a custom microcode array.
2. Description of the Related Art
One of the problems with semiconductor test techniques is associated with the usage of automatic test equipment (ATE) to apply the test patterns at the device's external inputs and measure the responses at the device's external outputs. This approach does not provide a means to adequately detect all of the device's internal defects. Direct access to the internal structures of a device is necessary. This need has led to the development of design-for-test (DFT) and array built-in self-test (ABIST) techniques and methods.
DFT techniques include design rules and constraints aimed at increasing the testability of a design through increased internal test controllability and observability. A well-known form of DFT is level sensitive scan design (LSSD), which involves modifying the internal storage elements of a device such that, in a test mode, the storage elements form individual stages of a shift register for scanning in test data stimuli and scanning out test responses.
One basic method of testing a VLSI device is by the application of the LSSD Flush and Scan test. The LSSD Flush and Scan test are used to determine if scan chains are operational to continue further LSSD testing. If the Flush and Scan tests fail, no further testing is required in a particular test mode or chip configuration, since all subsequent LSSD tests would also fail, therefore, a typical manufacturing test flow would skip out at that point. A current art method of testing a custom microcode array is an Array Built-In Self-Test (ABIST), which is used to provide at-speed testing of embedded arrays and memory elements. For the ABIST test, a controller based on a programmable-state machine is used to algorithmically generate a variety of memory test sequences.